
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
General Description
General Description
The 2Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic
random-access memory containing 2,147,483,648 bits. The LPDDR2-S4 device is inter-
nally configured as an eight-bank DRAM. Each of the x16’s 268,435,456-bit banks is or-
ganized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit
banks is organized as 16,384 rows by 512 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-
preted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS, DQS# and CK, CK# respectively, unless
specifically stated otherwise. “BA” includes all BA pins used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
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